Note: The AMD
Versal adaptive SoC DMA and Bridge Subsystem for PCIe IP is implemented in a modular IP architecture. This means that GTs, PCIe IP, and the subsystem IP are implemented separately. The interface signals
between GTs and PCIe IP going to a subsystem IP are not listed in this
guide. These interface signals are found in
Versal Adaptive SoC Integrated Block for PCI Express
LogiCORE IP Product Guide (PG343). The signals below apply to the subsystem only.
The AMD XDMA Subsystem connects directly to the integrated block for PCIe. The datapath interfaces to the PCIe integrated block IP are 64, 128, 256 or 512-bits wide, and runs at up to 250 MHz depending on the configuration of the IP. The datapath width applies to all data interfaces except for the AXI4-Lite interfaces. AXI4-Lite interfaces are fixed at 32-bits wide.
Ports associated with this subsystem are described in the following tables.