Queue Status Ports - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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2.0 English

All marker responses are sent out through this interface. If the IP is configured in an internal mode (no descriptor bypass), there are some marker responses sent out on this interface for packet completion. You can ignore this interface or set the mrkr_dis signal bit in the context settings.

Table 1. Queue Status Ports
Port Name I/O Description
qsts_out_op[7:0] O Opcode This indicates the type of packet being issued. Encoding of this field is as follows.

0x0: CMPT Marker Response

0x1: H2C-ST Marker Response

0x2: C2H-MM Marker Response

0x3: H2C-MM Marker Response

0x4-0xff: reserved

qsts_out_data[63:0] O The data field for the individual opcodes are defined in the tables Table 1 and Table 2.
qsts_out_port_id[2:0] O Port ID
qsts_out_qid[11:0] O Queue ID
qsts_out_vld O Queue status valid
qsts_out_rdy I Queue status ready. Ready must be tied to 1 so status output will not be blocked. Even if this interface is not used, the ready port must be tied to 1.