SGDMA Identifier Registers (0x00) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2024-11-22
Version
2.0 English
Table 1. SGDMA Identifier Registers (0x00)
Bit Index Default Access Type Description
31:20 12’h1fc RO Subsystem identifier
19:16 4’h6 RO SGDMA Target
15:8 8’h0 RO Reserved
7:0 8'h04 RO

Version

8'h01: 2015.3 and 2015.4

8'h02: 2016.1

8'h03: 2016.2

8'h04: 2016.3

8'h05: 2016.4

8'h06: 2017.1 to current release