AXI4 Memory Mapped Default Example Design - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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2.0 English

The following figure shows the AXI4 Memory Mapped (AXI-MM) interface as the default design. The example design gives 4 kilobytes (KB) block RAM on user design with AXI4 MM interface. For H2C transfers, the XDMA Subsystem reads data from host and writes to block RAM in the user side. For C2H transfers, the XDMA Subsystem reads data from block RAM and writes to host memory. The example design from the IP catalog has only 4 KB block RAM; you can regenerate the subsystem for larger block RAM size, if wanted.

Figure 1. AXI-MM Default Example Design