| Signal Name | Direction | Description |
|---|---|---|
| m_axil_araddr[31:0] | O | This signal is the address for a memory mapped read to the user logic from the host. |
| m_axil_arprot[2:0] | O | 3’h0 |
| m_axil_arvalid | O | The assertion of this signal means there is a valid read request to the address on m_axil_araddr. |
| m_axil_arready | I | Master read address ready. |
| m_axil_rdata[31:0] | I | Master read data. |
| m_axil_rresp | I | Master read response. |
| m_axil_rvalid | I | Master read valid. |
| m_axil_rready | O | Master read ready. |