Example Design Registers - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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2.0 English
Table 1. Example Design Registers
Registers Address Description
C2H_ST_QID (0x000) 0x000 AXI-ST C2H Queue id
C2H_ST_LEN (0x004) 0x004 AXI-ST C2H transfer length
C2H_CONTROL_REG (0x008) 0x008 AXI-ST C2H pattern generator control
H2C_CONTROL_REG (0x00C) 0x00C AXI-ST H2C Control
H2C_STATUS (0x010) 0x010 AXI-ST H2C Status
C2H_STATUS (0x018) 0x018 AXI-ST C2H Status
C2H_PACKET_COUNT (0x020) 0x020 AXI-ST C2H number of packets to transfer
C2H_COMPLETION_DATA_0 (0x030) to C2H_COMPLETION_DATA_7 (0x04C) 0x4C-0x030 AXI-ST C2H completion data
C2H_COMPLETION_SIZE (0x050) 0x050 AXI-ST completion data type
SCRATCH_REG0 (0x060) 0x060 Scratch register 0
SCRATCH_REG1 (0x064) 0x064 Scratch register 1
C2H_PACKETS_DROP (0x088) 0x088 AXI-ST C2H Packets drop count
C2H_PACKETS_ACCEPTED (0x08C) 0x08C AXI-ST C2H Packets accepted count
DESCRIPTOR_BYPASS (0x090) 0x090 C2H and H2C descriptor bypass loopback
USER_INTERRUPT (0x094) 0x094 User interrupt, vector number, function number
USER_INTERRUPT_MASK (0x098) 0x098 User interrupt mask
USER_INTERRUPT_VECTOR (0x09C) 0x09C User interrupt vector
DMA_CONTROL (0x0A0) 0x0A0 DMA control
VDM_MESSAGE_READ (0x0A4) 0x0A4 VDM message read