H2C Channel Control (0x04) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2024-06-03
Version
2.0 English
Table 1. H2C Channel Control (0x04)
Bit Index Default Access Type Description
31:28 Reserved
27 1’b0 RW When set write back information for C2H in AXI-Stream mode is disabled, default write back is enabled.
26 0x0 RW pollmode_wb_enable

Poll mode writeback enable.

When this bit is set the DMA writes back the completed descriptor count when a descriptor with the Completed bit set, is completed.

25 1’b0 RW non_inc_mode

Non-incrementing address mode. Applies to m_axi_araddr interface only.

24     Reserved
23:19 5’h0 RW ie_desc_error

Set to all 1s (0x1F) to enable logging of Status.Desc_error and to stop the engine if the error is detected.

18:14 5’h0 RW

ie_write_error

Set to all 1s (0x1F) to enable logging of Status.Write_error and to stop the engine if the error is detected.

13:9 5’h0 RW

ie_read_error

Set to all 1s (0x1F) to enable logging of Status.Read_error and to stop the engine if the error is detected.

8:7 Reserved
6 1’b0 RW ie_idle_stopped

Set to 1 to enable logging of Status.Idle_stopped

5 1’b0 RW ie_invalid_length

Set to 1 to enable logging of Status.Invalid_length

4 1’b0 RW ie_magic_stopped

Set to 1 to enable logging of Status.Magic_stopped

3 1’b0 RW ie_align_mismatch

Set to 1 to enable logging of Status.Align_mismatch

2 1’b0 RW ie_descriptor_completed

Set to 1 to enable logging of Status.Descriptor_completed

1 1’b0 RW ie_descriptor_stopped

Set to 1 to enable logging of Status.Descriptor_stopped

0 1’b0 RW Run

Set to 1 to start the SGDMA engine. Reset to 0 to stop transfer; if the engine is busy it completes the current descriptor.

  1. The ie_* register bits are interrupt enabled. When these bits are set and the corresponding condition is met, status will be logged in the H2C Channel Status (0x40). When the proper interrupt masks are set (per H2C Channel Interrupt Enable Mask (0x90)), the interrupt will be generated.