Available Tests - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2024-06-03
Version
2.0 English

The following table describes the tests provided for simulation. These tests are selected based on the QDMA IP configuration. For example, if the AXI4-MM only option is selected, the qdma_mm_test0 test case is selected and will be executed during simulation.

Table 1. Test Case
Option Test Name Language Description
AXI4-MM only qdma_mm_test0 Verilog
  1. The test bench initializes the queue and performs the AXI4-MM transfer in the H2C direction.
  2. Then, the test bench initializes the queue and performs the AXI4-MM transfer in the C2H direction.

The test bench compares the write data with the read data for correctness.

AXI4-ST only qdma_st_test0 Verilog
  1. The test bench initializes the queue, performs the AXI4-ST transfer in H2C direction, and then checks for data correctness.
  2. The test bench initializes the queue, performs the AXI4-ST transfer in the C2H direction, and then checks data for correctness.
AXI4-MM and AXI4-ST with completion qdma_mm_st_test0 Verilog
  1. The test bench initializes the queue and performs the AXI4-MM transfer in the H2C direction. Then, the test bench initializes the queue, performs AXI4-MM in C2H direction, and compares the data for correctness.
  2. The test bench initializes the queue, performs the AXI4-ST transfer in the H2C direction, and then checks data for correctness.
  3. Then, the test bench initializes the and performs AXI4-ST in the C2H direction and check data for correctness.

This test is a combination of test cases qdma_mm_test0 and qdma_st_test0.