C2H Channel 0-3 AXI4-Stream Interface Signals - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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Table 1. C2H Channel 0-3 AXI4-Stream Interface Signals
Signal Name 1 Direction Description
s_axis_c2h_tready_x O Assertion of this signal indicates that the DMA is ready to accept data. Data is transferred across the interface when s_axis_c2h_tready and s_axis_c2h_tvalid are asserted in the same cycle. If the DMA deasserts the signal when the valid signal is High, the user logic must keep the valid signal asserted until the ready signal is asserted.
s_axis_c2h_tlast_x I The user logic asserts this signal to indicate the end of the DMA packet.


I Transmits data from the user logic to the DMA.
s_axis_c2h_tvalid_x I The user logic asserts this whenever it is driving valid data on s_axis_c2h_tdata.


I Parity bits. This port is enabled only in Propagate Parity mode.


I The tkeep signal tells how many bytes are valid for each beat. It must be asserted for all beets except when tlast is asserted. You must specify how many bytes are valid when tlast is asserted.
  1. _x in the signal name changes based on the channel number 0, 1, 2, and 3. For example, for channel 0 use the m_axis_c2h_tready_0 port, and for channel 1 use the m_axis_c2h_tready_1 port.