| Bit Index | Default | Access Type | Description |
|---|---|---|---|
| 23:19 | 5’h0 | RW1C |
descr_error[4:0] Reset (0) on setting the Control register Run bit. Bit position: 4:Unexpected completion 3: Header EP 2: Parity error 1: Completer abort 0: Unsupported request |
| 13:9 | 5’h0 | RW1C |
read_error[4:0] Reset (0) on setting the Control register Run bit. Bit position: 4-2: Reserved 1: Slave error 0: Decode error |
| 8:7 | Reserved | ||
| 6 | 1’b0 | RW1C |
idle_stopped Reset (0) on setting the Control register Run bit. Set when the engine is idle after resetting the Control register Run bit if the Control register ie_idle_stopped bit is set. |
| 5 | 1’b0 | RW1C |
invalid_length Reset on setting the Control register Run bit. Set when the descriptor length is not a multiple of the data width of an AXI4-Stream channel and the Control register ie_invalid_length bit is set. |
| 4 | 1’b0 | RW1C |
magic_stopped Reset on setting the Control register Run bit. Set when the engine encounters a descriptor with invalid magic and stopped if the Control register ie_magic_stopped bit is set. |
| 3 | 13’b0 | RW1C |
align_mismatch Source and destination address on descriptor are not properly aligned to each other. |
| 2 | 1’b0 | RW1C |
descriptor_completed Reset on setting the Control register Run bit. Set after the engine has completed a descriptor with the COMPLETE bit set if the Control register ie_descriptor_completed bit is set. |
| 1 | 1’b0 | RW1C |
descriptor_stopped Reset on setting the Control register Run bit. Set after the engine completed a descriptor with the STOP bit set if the Control register ie_magic_stopped bit is set. |
| 0 | 1’b0 | RO |
Busy Set if the SGDMA engine is busy. Zero when it is idle. |