| m_axil_awaddr[31:0] |
O |
This signal is the address for a memory mapped write to
the user logic from the host. |
| m_axil_awprot[2:0] |
O |
3’h0 |
| m_axil_awvalid |
O |
The assertion of this signal means there is a valid write
request to the address on m_axil_awaddr. |
| m_axil_awready |
I |
Master write address ready. |
| m_axil_wdata[31:0] |
O |
Master write data. |
| m_axil_wstrb |
O |
Master write strobe. |
| m_axil_wvalid |
O |
Master write valid. |
| m_axil_wready |
I |
Master write ready. |
| m_axil_bvalid |
I |
Master response valid. |
| m_axil_bready |
O |
Master response ready. |