User IRQ Example Design - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2023-11-10
Version
2.0 English

The user IRQ example design enables the host to connect to the AXI4-Lite Master interface along with the default XDMA Subsystem example design. In the example design, the User Interrupt generator module and an external block RAM is integrated on this AXI4-Lite interface. The host can use this interface to generate the user IRQ by writing to the register space of the User Interrupt generator module and can also read/write to the external 1K block RAM. The following figure shows the example design.

The example design can be generated using the following Tcl command.

set_property -dict [list CONFIG.usr_irq_exdes {true}] [get_ips <ip_name>]
Figure 1. User IRQ Example Design

The register description is found in the following table.

Table 1. Example Design Registers
Register Offset Register Name Access Type Description
0x00 Scratch Pad RW Scratch Pad
0x04 DMA BRAM Size RO User Memory Size connected to XDMA.

Memory size = (2[7:4]) ([3:0]Byte)

[7:4] – denotes the size in powers of 2.

  • 0 – 1
  • 1 – 2
  • 2 – 4
  • 8 – 256
  • 9 – 512

[3:0] – denotes unit.

  • 0 – Byte
  • 1 – KB
  • 2 – MB
  • 3 – GB

For example, if the register value is 21, the size is 4 KB. If the register value is 91, the size is 512 KB.

0x08 Interrupt Control Register RW

Interrupt control register (write 1 to generate interrupt).

Interrupt Status register corresponding bit must be 1 (ready) to generate interrupt. Also, reset the corresponding bit after ISR is served.

0x0C Interrupt Status Register RO

Interrupt Status.

1: ready

0: Interrupt generation in progress

Note: In case of Legacy interrupt, the Interrupt Control Register (0x08) value for the corresponding interrupt bit should only be cleared after the ISR is served as this can be used by the host to determine the interrupt source.