| Port Name | I/O | Description |
|---|---|---|
| sys_clk | I | Should be driven by the ODIV2 port of reference clock IBUFDS_GTE4. See the Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343) . |
| sys_clk_gt | I | PCIe reference clock. Should be driven from the port of reference clock IBUFDS_GTE4. See the Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343) . |
| sys_rst_n | I | Reset from the PCIe edge connector reset signal. |
| pci_exp_txp [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] | O | PCIe TX serial interface. |
| pci_exp_txn [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] | O | PCIe TX serial interface. |
| pci_exp_rxp [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] | I | PCIe RX serial interface. |
| pci_exp_rxn [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] | I | PCIe RX serial interface. |
| user_lnk_up | O | Output active-High identifies that the PCI Express core is linked up with a host device. |
| axi_aclk | O | User clock out. PCIe derived clock output for for all interface signals output from and input to QDMA. Use this clock to drive inputs and gate outputs from QDMA. |
| axi_aresetn | O | User reset out. AXI reset signal synchronous with the clock provided on the axi_aclk output. This reset should drive all corresponding AXI Interconnect aresetn signals. |
| soft_reset_n | I | Soft reset (active-Low). Use this port to assert reset and reset the DMA logic. This will reset only the DMA logic. User should assert and de-assert this port. |
| phy_ready | O | Phy ready out status. |
| csr_prog_done | O | This port is enabled only when the AXI-Lite CSR Slave Interface
option is selected in the Basic tab in the IP customization GUI. This port indicates
whether access to AXI Lite CSR interface is available. 1'b0: The AXI Lite CSR Slave interface is not accessible. 1'b1: The AXI Lite CSR Slave interface is accessible. |
All AXI interfaces are clocked out and in by the axi_aclk signal. You are
responsible for using axi_aclk to driver all signals into the DMA.