AXI4 Memory Mapped Read Address Interface Signals - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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Table 1. AXI4 Memory Mapped Read Address Interface Signals
Signal Name Direction Description


O This signal is the address for a memory mapped read to the user logic from the DMA.
m_axi_arid [ID_WIDTH-1:0] O Standard AXI4 description, which is found in the AXI4 Protocol Specification.
m_axi_arlen[7:0] O Master read burst length.
m_axi_arsize[2:0] O Master read burst size.
m_axi_arprot[2:0] O 3’h0
m_axi_arvalid O The assertion of this signal means there is a valid read request to the address on m_axi_araddr.
m_axi_arready I Master read address ready.
m_axi_arlock O 1’b0
m_axi_arcache[3:0] O 4’h0
m_axi_arburst O Master read burst type.