Note: The AMD
Versal Adaptive SoC DMA and Bridge Subsystem for PCIe IP is implemented in a modular IP architecture. This means that
GTs, PCIe IP, and the subsystem IP are implemented separately.
The interface signals between GTs and PCIe IP going to a
subsystem IP are not listed in this guide. These interface signals are found in
Versal Adaptive SoC Integrated Block for PCI Express
LogiCORE IP Product Guide (PG343). The signals below apply to
the subsystem only.
The interface signals for the subsystem are described in the following tables.