IRQ Block User Vector Number (0x88) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2023-11-10
Version
2.0 English

If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In legacy interrupts only the 2 LSB of each field should be used to map to INTA, B, C, or D.

Table 1. IRQ Block User Vector Number (0x88)
Bit Index Default Access Type Description
28:24 5’h0 RW

vector 11

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[11].

20:16 5’h0 RW

vector 10

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[10].

12:8 5’h0 RW

vector 9

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[9].

4:0 5’h0 RW

vector 8

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[8].