AMD LogiCORE™ IP Facts Table | |
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Subsystem Specifics | |
Supported Device Family 1 | AMD Versal™ adaptive SoC |
Supported User Interfaces | AXI4 Memory Map, AXI4-Lite, AXI4-Stream |
Resources |
QDMA and AXI Bridge
Subsystems: Performance and Resource Utilization
XDMA Subsystem: Performance and Resource Utilization |
Provided with Subsystem | |
Design Files | Encrypted System Verilog |
Example Design | Verilog |
Test Bench | Verilog |
Constraints File | Xilinx Design Constraints File (XDC) |
Simulation Model | Verilog |
Supported S/W Driver 2 |
QDMA Subsystem: x86 Linux Kernel and x86 Linux DPDK drivers for endpoint designs AXI Bridge Subsystems: ARM Linux Kernel and ARM Baremetal drivers for root port designs XDMA Subsystem: x86 Linux Kernel driver for endpoint designs |
Tested Design Flows 3 | |
Design Entry | AMD Vivado™ Design Suite |
Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
Synthesis | Vivado Synthesis |
Support | |
Release Notes and Known Issues | Master Answer Record: AR 75397 |
All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
Support web page | |
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