Config Write Flush Timeout (0x60)

Config Write Flush Timeout (0x60) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID

PG344

Release Date

2024-06-03

Version

2.0 English

Table 1. Config Write Flush Timeout (0x60)
Bit Index	Default	Access Type	Description
4:0	5’h0	RW	Write Flush Timeout Applies to AXI4-Stream C2H channels. This register specifies the number of clock cycles a channel waits for data before flushing the write data it already received from PCIe. This action closes the descriptor and generates a writeback. A value of 0 disables the timeout. The timeout value in clocks = 2^value.