H2C Channel 0-3 AXI4-Stream Interface Signals - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID: PG344
Release Date: 2024-11-22
Version: 2.0 English

Table 1. H2C Channel 0-3 AXI4-Stream Interface Signals
Signal Name¹	Direction	Description
m_axis_h2c_tready_x	I	Assertion of this signal by the user logic indicates that it is ready to accept data. Data is transferred across the interface when m_axis_h2c_tready and m_axis_h2c_tvalid are asserted in the same cycle. If the user logic deasserts the signal when the valid signal is High, the DMA keeps the valid signal asserted until the ready signal is asserted.
m_axis_h2c_tlast_x	O	The DMA asserts this signal in the last beat of the DMA packet to indicate the end of the packet.
m_axis_h2c_tdata_x [DATA_WIDTH-1:0]	O	Transmit data from the DMA to the user logic.
m_axis_h2c_tvalid_x	O	The DMA asserts this whenever it is driving valid data on m_axis_h2c_tdata.
m_axis_h2c_tuser_x [DATA_WIDTH/8-1:0]	O	Parity bits. This port is enabled only in Propagate Parity mode.
m_axis_h2c_tkeep_x [DATA_WIDTH/8-1:0]	O	The tkeep signal specifies how many bytes are valid when tlast is asserted.
_x in the signal name changes based on the channel number 0, 1, 2, and 3. For example, for channel 0 use the m_axis_h2c_tready_0 port, and for channel 1 use the m_axis_h2c_tready_1 port.