Simulation Design Overview - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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2.0 English

For the simulation design, transactions are sent from the Root Port Model to the Bridge core configured as an Endpoint and processed inside the AXI Block RAM controller design.

The following figure illustrates the simulation design provided with the AXI Bridge subsystem.

Figure 1. Example Design Block Diagram

The example design supports Verilog as the target language.

For comprehensive information about AMD Vivado™ simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900).