The Root Port Model consists of these blocks:
-
dsport(Root Port) -
usrapp_tx -
usrapp_rx -
usrapp_com(Verilog only)
The usrapp_tx and usrapp_rx blocks interface with the
dsport block for transmission and reception of TLPs to/from the
Endpoint Design Under Test (DUT). The Endpoint DUT consists of the Endpoint for PCIe and the PIO design (displayed) or customer design.
The usrapp_tx block sends TLPs to the dsport block for
transmission across the PCI Express Link to the Endpoint DUT. In turn, the Endpoint DUT
device transmits TLPs across the PCI Express Link to the dsport block,
which are subsequently passed to the usrapp_rx block. The
dsport and core are responsible for the data link layer and
physical link layer processing when communicating across the PCI Express logic. Both
usrapp_tx and usrapp_rx use the
usrapp_com block for shared functions, for example, TLP processing
and log file outputting. Transaction sequences or test programs are initiated by the
usrapp_tx block to stimulate the Endpoint device fabric interface.
TLP responses from the Endpoint device are received by the usrapp_rx
block. Communication between the usrapp_tx and
usrapp_rx blocks allow the usrapp_tx block to
verify correct behavior and act accordingly when the usrapp_rx block
has received TLPs from the Endpoint device.