Example Design Elements - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2024-06-03
Version
2.0 English

The core wrapper includes:

  • An example Verilog HDL or VHDL wrapper (instantiates the cores and example design).
  • A customizable demonstration test bench to simulate the example design.