AXI4 Memory Mapped Write Address Interface Signals - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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Table 1. AXI4 Memory Mapped Write Address Interface Signals
Signal Name Direction Description


O This signal is the address for a memory mapped write to the user logic from the DMA.


O Master write address ID.
m_axi_awlen[7:0] O Master write address length.
m_axi_awsize[2:0] O Master write address size.
m_axi_awburst[1:0] O Master write address burst type.
m_axi_awprot[2:0] O 3’h0
m_axi_awvalid O The assertion of this signal means there is a valid write request to the address on m_axi_araddr.
m_axi_awready I Master write address ready.
m_axi_awlock O 1’b0
m_axi_awcache[3:0] O 4’h0