The AMD Versal™ adaptive SoC DMA and Bridge Subsystems for PCIe® provides a rich set of options for high performance data transfer between an AMD Versal™ adaptive SoC and other devices using the widely deployed and industry standard PCI Express system architecture.
Figure 1. Versal Adaptive SoC DMA and Bridge Subsystem for PCIe
These subsystems are built upon the robust and flexible programmable logic integrated block for PCI Express (PL PCIE) as shown in the figure above, and expands the integrated block capabilities through a soft IP implemented in the AMD Versal adaptive SoC programmable logic. There are three subsystems available namely, QDMA Subsystem, AXI Bridge Subsystem, and XDMA Subsystem.