AXI4 Memory Mapped Read Interface Signals - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2023-11-10
Version
2.0 English
Table 1. AXI4 Memory Mapped Read Interface Signals
Signal Name Direction Description
m_axi_rdata [DATA_WIDTH-1:0] I Master read data.
m_axi_rid [ID_WIDTH-1:0] I Master read ID.
m_axi_rresp[1:0] I Master read response.
m_axi_rlast I Master read last.
m_axi_rvalid I Master read valid.
m_axi_rready O Master read ready.
m_axi_ruser

[DATA_WIDTH/8-1:0]

I Parity ports for read interface. This port is enabled only in Propagate Parity mode.