QDMA_PF_MAILBOX (0x22400) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2024-06-03
Version
2.0 English
Table 1. QDMA_PF_MAILBOX (0x22400) Register Space
Register Address Description
Function Status Register (0x22400) 0x22400 Status bits
Function Command Register (0x22404) 0x22404 Command register bits
Function Interrupt Vector Register (0x22408) 0x22408 Interrupt vector register
Target Function Register (0x2240C) 0x2240C Target Function register
Function Interrupt Vector Register (0x22410) 0x22410 Interrupt Control Register
RTL Version Register (0x22414) 0x22414 RTL Version Register
PF Acknowledgment Registers (0x22420-0x2243C) 0x22420-0x2243C PF acknowledge
FLR Control/Status Register (0x22500) 0x22500 FLR control and status
Incoming Message Memory (0x22C00-0x22C7C) 0x22C00-0x22C7C Incoming message (128 bytes)
Outgoing Message Memory (0x23000-0x2307C) 0x23000-0x2307C Outgoing message (128 bytes)

Mailbox Addressing

PF addressing
Addr = PF_Bar_offset + CSR_addr
VF addressing
Addr = VF_Bar_offset + VF_Start_offset + VF_offset + CSR_addr