The descriptor fetch engine can be bypassed on a per channel basis through
AMD Vivado™
IDE parameters. A channel with
descriptor bypass enabled accepts descriptor from its respective c2h_dsc_byp or h2c_dsc_byp bus. Before the
channel accepts descriptors, the Control register Run bit must be set. The
NextDescriptorAddress and NextAdjacentCount, and Magic descriptor fields are not used
when descriptors are bypassed. The ie_descriptor_stopped
bit in Control register bit does not prevent the user logic from writing additional
descriptors. All descriptors written to the channel are processed, barring writing of
new descriptors when the channel buffer is full.
When XDMA is configured in descriptor bypass mode, there is an 8 deep descriptor FIFO which is common for all descriptor channels from user.