The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 11/22/2024 Version 2.0 | |
| Unsupported Features | Updated section. |
| AXI4-Lite Slave CSR Ports | Updated section. |
| Minimum Device Requirements | Updated table. |
| Basic Tab | Updated section. |
| AXI BARs Tab | Updated section. |
| Traffic Manager Output Interface | Updated section. |
| Function Level Reset | Updated section. |
| AXI4-Lite Slave Ports | Updated table. |
| AXI4-Lite Slave CSR Ports | Updated table. |
| AXI4-Lite Slave CSR Interface | Updated table. |
| Descriptor Bypass | Updated section. |
| PCIe BARs Tab | Updated Base Address Register Overview. |
| 06/03/2024 Version 2.0 | |
| Features of the DMA and Bridge Subsystem | Updated section. |
| QDMA Subsystem Limitations | Updated section. |
| Minimum Device Requirements | Updated tables. |
| GT Quad Locations | Updated table. |
| 11/10/2023 Version 2.0 | |
| Maximum Supported Link Rates and Widths | Updated section. |
| IP Facts | Updated supported software drivers. |
| Features of the DMA and Bridge Subsystem | Updated features. |
| Minimum Device Requirements | Updated tables. |
| Features | Updated features. |
| Completion Engine | Updated section. |
| QDMA Subsystem Limitations | Updated section. |
| Performance and Resource Utilization | Updated section. |
| Completion Engine | Added a note. |
| User Interrupts | Updated User Interrupts Port Descriptions table. |
| AXI Stream Performance Example Design | Updated section. |
| 05/16/2023 Version 2.0 | |
| Features | Added a note. |
| Marker Response | Updated section. |
| 11/02/2022 Version 2.0 | |
| Minimum Device Requirements | Updated PL PCIE5 with QDMA or Bridge Soft IP Subsystem Maximum Configurations table. |
| 10/19/2022 Version 2.0 | |
| General updates | Entire document. |
| Modular IP Architecture | Added an AR link. |
| Resets | Updated to add a command. |
| Context Programming | Added bit field description for 4:1. |
| Customizing and Generating the Example Design | Added a figure. |
| 05/20/2022 Version 1.0 | |
| AXI4-Stream C2H Ports | Updated AXI4-Stream C2H Port Descriptions table. |
| Function Map Table | Updated section. |
| AXI4-Lite Master Ports | Updated Config AXI4-Lite Memory Mapped Read Master Interface Port Descriptions table. |
| AXI4-Stream C2H Ports | Updated AXI4-Stream C2H Port Descriptions table. |
| QDMA VF Address Register Space | Updated QDMA VF Address Register Space table. |
| Descriptor Bypass Mode | Updated section. |
| 04/26/2022 Version 1.0 | |
| General updates | Updated for Versal Premium adaptive SoC support. |
| Debug Guide | New section. |
| 12/20/2021 Version 1.0 | |
| Minimum Device Requirements | Added new section. |
| C2H Channel 0-3 AXI4-Stream Interface Signals | Added m_axis_h2c_tkeep_x. |
| Basic Tab | Added recommendations regarding selecting the correct GT starting quad before lane rate and width. |
| QDMA Global Ports | Added csr_prog_done. |
| AXI4-Stream C2H Ports | Updated s_axis_c2h_ctrl_ecc[6:0]. |
| User Interrupts | Update usr_irq_in_vec. |
| PCIe MISC Tab in Root Port Mode | New content added. |
| Debugging chapters | Added link to debugging answer record. |
| Upgrading | Updated link for migration information. |
| Limitations | Updated content, and moved to an appendix. |
| 04/27/2021 Version 1.0 | |
| Initial release. | N/A |