IRQ Block Channel Interrupt Enable Mask (0x10) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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Table 1. IRQ Block Channel Interrupt Enable Mask (0x10)
Bit Index Default Access Type Description
[NUM_CHNL-1:0] ‘h0 RW


Engine Interrupt Enable Mask. One bit per read or write engine.

0: Prevents an interrupt from being generated when interrupt source is asserted. The position of the H2C bits always starts at bit 0. The position of the C2H bits is the index above the last H2C index, and therefore depends on the NUM_H2C_CHNL parameter.

1: Generates an interrupt on the rising edge of the interrupt source. If the enmask bit is set and the source is already set, an interrupt is also be generated.