| s_axil_csr_awaddr[31:0] |
I |
This signal is the address for a memory mapped
write to the DMA from the user logic.
| Mode |
Bit[28] |
Bit[15] |
| QDMA CSR register |
0 |
1 |
| Bridge register |
0 |
0 |
Other combinations of 28-Bit and 25-Bit are not
valid.
|
| s_axil_csr_awvalid |
I |
The assertion of this signal means there is a
valid write request to the address on s_axil_csr_awaddr. |
| s_axil_csr_awprot[2:0] |
I |
Protection type.(unused) |
| s_axil_csr_awready |
O |
Slave write address ready. |
| s_axil_csr_wdata[31:0] |
I |
Slave write data. |
| s_axil_csr_wstrb[3:0] |
I |
Slave write strobe. |
| s_axil_csr_wvalid |
I |
Slave write valid. |
| s_axil_csr_wready |
O |
Slave write ready. |
| s_axil_csr_bvalid |
O |
Slave write response valid. |
| s_axil_csr_bresp[1:0] |
O |
Slave write response. |
| s_axil_csr_bready |
I |
Save response ready. |