AXI4-Lite Slave CSR Interface - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2024-06-03
Version
2.0 English
Table 1. AXI4-Lite Slave CSR Signals
Signal Name I/O Description
s_axil_csr_awaddr[31:0] I This signal is the address for a memory mapped write to the DMA from the user logic.

s_axil_csr_awaddr[15]:

1'b1 – QDMA CSR register

1'b0 – Bridge register
s_axil_csr_awvalid I The assertion of this signal means there is a valid write request to the address on s_axil_csr_awaddr.
s_axil_csr_awprot[2:0] I Protection type.(unused)
s_axil_csr_awready O Slave write address ready.
s_axil_csr_wdata[31:0] I Slave write data.
s_axil_csr_wstrb[3:0] I Slave write strobe.
s_axil_csr_wvalid I Slave write valid.
s_axil_csr_wready O Slave write ready.
s_axil_csr_bvalid O Slave write response valid.
s_axil_csr_bresp[1:0] O Slave write response.
s_axil_csr_bready I Save response ready.