PCIe MISC Tab in Root Port Mode - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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2.0 English

The PCIe Miscellaneous tab options for the AXI Bridge subsystem are shown in the following figure.

Figure 1. PCIe Miscellaneous Tab

The options are defined as follows:

Link Status Register
By default, Enable Slot Clock Configuration is selected. This means that the slot configuration bit is enabled in the link status register.
Enable PM_L23 Entry