AXI4-Stream C2H Write Completion Ports - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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Table 1. AXI-ST C2H Write Completion Port Descriptions
Port Name I/O Description
axis_c2h_dmawr_cmp O This signal is asserted when the last data payload write request of the packet gets the write completion. It is one pulse per packet.