Initial Debug of the XDMA - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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2.0 English

Status bits out of each engine can be used for initial debug of the subsystem. Per channel interface provides important status to the user application.

Table 1. Initial Debug of the Subsystem
Bit Index Field Description
7 NA Reserved
6 Run Channel control register run bit.
5 IRQ_Pending Asserted when the channel has interrupt pending.
4 Packet_Done On an AXIST interface this bit indicates the last data indicated by the EOP bit has been posted.
3 Descriptor_Done A descriptor has finished transferring data from the source and posted it to the destination.
2 Descriptor_Stop Descriptor_Done and Stop bit set in the descriptor.
1 Descriptor_Completed Descriptor_Done and Completed bit set in the descriptor.
0 Busy Channel descriptor buffer is not empty or DMA requests are outstanding.

Read H2C/C2H Channel status register 0x40 to see if there are any errors registered. Also check if bit [0] busy bit is set to 1. If it is set to 1, then DMA is waiting for some user event to happen. Read H2C/C2H Channel Completed Descriptor Count (0x48) to see how many descriptors are fetched by the DMA, and compare it with what it should be, based on the DMA transfer. If MSIX interrupt mode transfers have issues, try in poll mode to see if transfers go through.

Software Debug

Using AMD driver can help you debug some issues. Compile the driver in DEBUG mode which enables verbose mode and prints more information for a transfer. Check the dmesg for a run to see all the steps are listed for a dma transfer.

Descriptor used for a transfer is printed so check the descriptor to make sure source/destination address is listed correctly. Check the transfer length for that descriptor is correct. Make sure that the descriptor magic word is correct. Follow the dmesg log to see if there are any errors recorded.

ILA Debug

You can add ILA on the output and input of the IP on the AXI side to see if any abnormal transfers are happening. You can check if the packet sent into the IP is proper and it matches with what is expected. You can add ILA in the PCIe core CQ/CC and RQ/RC interface, this lets you know how the DMA IP is fetching the descriptor and data. You need to use all the above suggestions to figure out the issue.