A Completion Timeout occurs when a completion (Cpl) or completion with data (CplD)
TLP is not returned after an AXI to PCIe memory read
request, or after a PCIe Configuration Read/Write request. For PCIe Configuration Read/Write request, completions must complete within
the C_COMP_TIMEOUT parameter selected value from the
time the request is issued. For PCIe Memory Read request, completions must complete
within the value set in the Device Control 2 register in the PCIe Configuration Space
register. When a completion timeout occurs, an OKAY response is asserted with all 0s and
1s data on the memory mapped AXI4 bus.