MSI and MSI-X Interrupts - 2.0 English

Asserting one or more bits of usr_irq_req causes the generation of an MSI or MSI-X interrupt if MSI or MSI-X is enabled. If both MSI and MSI-X capabilities are enabled, an MSI-X interrupt is generated.

After a usr_irq_req bit is asserted, it must remain asserted until the corresponding usr_irq_ack bit is asserted and the interrupt has been serviced and cleared by the Host. The usr_irq_ack assertion indicates the requested interrupt has been sent to the PCIe block. This will ensure the interrupt pending register within the IP remains asserted when queried by the Host's Interrupt Service Routine (ISR) to determine the source of interrupts. You must implement a mechanism in the user application to know when the interrupt routine has been serviced. This detection can be done in many different ways depending on your application and your use of this interrupt pin. This typically involves a register (or array of registers) implemented in the user application that is cleared, read, or modified by the Host software when an Interrupt is serviced.

Configuration registers are available to map usr_irq_req and DMA interrupts to MSI or MSI-X vectors. For MSI-X support, there is also a vector table and PBA table. The following figure shows the MSI interrupt.

Figure 1. MSI Interrupts

The following figure shows the MSI-X interrupt.

Figure 2. MSI-X Interrupts