C2H Channel Registers (0x1) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2024-06-03
Version
2.0 English

The C2H channel register space is described in this section.

Table 1. C2H Channel Register Space
Address (hex) Register Name
0x00 C2H Channel Identifier (0x00)
0x04 C2H Channel Control (0x04)
0x08 C2H Channel Control (0x08)
0x0C C2H Channel Control (0x0C)
0x40 C2H Channel Status (0x40)
0x44 C2H Channel Status (0x44)
0x48 C2H Channel Completed Descriptor Count (0x48)
0x4C C2H Channel Alignments (0x4C)
0x88 C2H Poll Mode Low Write Back Address (0x88)
0x8C C2H Poll Mode High Write Back Address (0x8C)
0x90 C2H Channel Interrupt Enable Mask (0x90)
0x94 C2H Channel Interrupt Enable Mask (0x94)
0x98 C2H Channel Interrupt Enable Mask (0x98)
0xC0 C2H Channel Performance Monitor Control (0xC0)
0xC4 C2H Channel Performance Cycle Count (0xC4)
0xC8 C2H Channel Performance Cycle Count (0xC8)
0xCC C2H Channel Performance Data Count (0xCC)
0xD0 C2H Channel Performance Data Count (0xD0)