C2H SGDMA Descriptor High Address (0x84) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2023-11-10
Version
2.0 English
Table 1. C2H SGDMA Descriptor High Address (0x84)
Bit Index Default Access Type Description
31:0 32’h0 RW

dsc_adr[63:32]

Upper bits of start descriptor address.

Dsc_adr[63:0] is the first descriptor address that is fetched after the Control register Run bit is set.