IRQ Block User Interrupt Enable Mask (0x0C) - 2.0 English - PG344

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2024-11-22
Version
2.0 English
Table 1. IRQ Block User Interrupt Enable Mask (0x0C)
Bit Index Default Access Type Description
W1C

user_int_enmask

Bit descriptions are the same as in IRQ Block User Interrupt Enable Mask (0x04).