AXI4 Memory Mapped with AXI4-Lite Slave Interface Example Design - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2024-06-03
Version
2.0 English

When the PCIe® to AXI4-Lite master and AXI4-Lite slave interface are enabled, the generated example design (shown in the following figure) has a loopback from AXI4-Lite master to AXI4-Lite slave. Typically, the user logic can use a AXI4-Lite slave interface to read/write XDMA Subsystem registers. With this example design, the host can use PCIe to AXI4-Lite Master (BAR0 address space) and read/write XDMA Subsystem registers, which is the same as using PCIe to DMA (BAR1 address space). This example design also shows PCIe to DMA bypass Interface (BAR2) enabled.

Figure 1. AXI-MM Example with AXI-Lite Slave Enabled