| Port Name | I/O | Description |
|---|---|---|
| dsc_crdt_in_vld | I | Valid. When asserted the user must be presenting valid data on the bus and maintain the bus values until both valid and ready are asserted on the same cycle. |
| dsc_crdt_in_rdy | O | Ready. Assertion of this signal indicates the DMA is ready to accept data from this bus. |
| dsc_crdt_in_dir | I | Indicates whether credits are for H2C or C2H descriptor ring.
0: H2C 1: C2H |
| dsc_crdt_in_fence | I |
If the fence bit is set, the credits are not coalesced, and the queue is guaranteed to generate a descriptor fetch before subsequent credit updates are processed. The fence bit should only be set for a queue that is enabled, and has both descriptors and credits available, otherwise a hang condition might occur. |
| dsc_crdt_in_qid [10:0] | I | The QID associated with the descriptor ring for the credits are being added. |
| dsc_crdt_in_crdt [15:0] | I | The number of descriptor credits that the user application is giving to QDMA to fetch descriptors from the host. |