Constraining the Subsystem - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2024-11-22
Version
2.0 English

Required Constraints

The QDMA subsystem requires the specification of timing and other physical implementation constraints to meet specified performance requirements for PCI Express® . These constraints are provided in a Xilinx Design Constraints (XDC) file. Pinouts and hierarchy names in the generated XDC correspond to the provided example design.

Important: If the example design top file is not used, copy the IBUFDS_GTE4 instance for the reference clock, IBUF Instance for sys_rst and also the location and timing constraints associated with them into your local design top.

To achieve consistent implementation results, an XDC containing these original, unmodified constraints must be used when a design is run through the AMD tools. For additional details on the definition and use of an XDC or specific constraints, see Vivado Design Suite User Guide: Using Constraints (UG903).

Constraints provided with the Integrated Block for PCIe® solution are tested in the hardware and provide consistent results. Constraints can be modified, but modifications should only be made with a thorough understanding of the effect of each constraint. Additionally, support is not provided for designs that deviate from the provided constraints.

Device, Package, and Speed Grade Selections

The device selection portion of the XDC informs the implementation tools which part, package, and speed grade to target for the design.

The device selection section always contains a part selection line, but can also contain part or package-specific options.

Clock Frequencies

For detailed information about clock requirements, see the Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343).

Clock Management

For detailed information about clock requirements, see the Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343).

Clock Placement

For detailed information about clock requirements, see the Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343).

Banking

This section is not applicable for this IP subsystem.

Transceiver Placement

This section is not applicable for this IP subsystem.

I/O Standard and Placement

This section is not applicable for this IP subsystem.

Relocating the Integrated Block Core

By default, the IP core-level constraints lock block RAMs, transceivers, and the PCIe block to the recommended location. To relocate these blocks, you must override the constraints for these blocks in the XDC constraint file. To do so:
  1. Copy the constraints for the block that needs to be overwritten from the core-level XDC constraint file.
  2. Place the constraints in the user XDC constraint file.
  3. Update the constraints with the new location.

The user XDC constraints are usually scoped to the top-level of the design; therefore, ensure that the cells referred by the constraints are still valid after copying and pasting them. Typically, you need to update the module path with the full hierarchy name.

Note: If there are locations that need to be swapped (that is, the new location is currently being occupied by another module), there are two ways to do this:
  • If there is a temporary location available, move the first module out of the way to a new temporary location first. Then, move the second module to the location that was occupied by the first module. Next, move the first module to the location of the second module. These steps can be done in XDC constraint file.
  • If there is no other location available to be used as a temporary location, use the reset_property command from Tcl command window on the first module before relocating the second module to this location. The reset_property command cannot be done in the XDC constraint file and must be called from the Tcl command file or typed directly into the Tcl Console.