Address Alignment - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2024-11-22
Version
2.0 English
Table 1. Address Alignment
Interface Type Datapath Width Address Restriction
AXI4 MM 64, 128, 256, 512 None
AXI4-Stream 64, 128, 256, 512 None
AXI4 MM fixed address 64 Source_addr[2:0] == Destination_addr[2:0] == 3’h0
AXI4 MM fixed address 128 Source_addr[3:0] == Destination_addr[3:0] == 4’h0
AXI4 MM fixed address 256 Source_addr[4:0] == Destination_addr[4:0] == 5’h0
AXI4 MM fixed address 512 Source_addr[5:0] == Destination_addr[5:0]==6'h0