Minimum Device Requirements - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID: PG344
Release Date: 2024-06-03
Version: 2.0 English

Table 1. PL PCIE4 with QDMA, Bridge, or XDMA Soft IP Subsystem Maximum Configurations (Versal Prime, Versal AI Core, Versal AI Edge)¹
Speed Grade	-1	-1	-2	-2	-2	-3
Voltage Grade	L (0.70V)	M (0.80V)	L (0.70V)	M (0.80V)	H (0.88V)	H (0.88V)
Gen1 (2.5 GT/s per lane)	x16	x16	x16	x16	x16	x16
Gen2 (5 GT/s per lane)	x16	x16	x16	x16	x16	x16
Gen3 (8 GT/s per lane)	x16	x16	x16	x16	x16	x16
Gen4 (16 GT/s per lane)	x8	x8	x8	x8	x8	x8
For target devices in -1L, -1M, and -2L grades, certain link configurations and placements can be challenging for timing closure, in addition to generally increased challenge for high performance DMA / Bridge soft IP solutions. The IP customization GUI, by default, limits access to those link configurations even though they appear in this table. For more information, see Answer Record 000035682 for general guidance on selecting link configurations and placements for easier timing closure, and for specific guidance on accessing link configurations which are access limited by default by the IP customization GUI. AMD advises you to review this answer record at the start of project planning and prior to the start of board schematic capture.

Table 2. PL PCIE5 with QDMA or Bridge Soft IP Subsystem Maximum Configurations (Versal Premium, Versal Prime, Versal HBM, Versal AI Core)¹
Speed Grade	-1	-1	-2	-2	-2	-3
Voltage Grade	L (0.70V)	M (0.80V)	L (0.70V)	M (0.80V)	H (0.88V)	H (0.88V)
Gen1 (2.5 GT/s per lane)	x16	x16	x16	x16	x16	x16
Gen2 (5 GT/s per lane)	x16	x16	x16	x16	x16	x16
Gen3 (8 GT/s per lane)	x16	x16	x16	x16	x16	x16
Gen4 (16 GT/s per lane)	x8	x8	x8	x8	x8	x8
Gen5 (32 GT/s per lane)²	N/A	N/A	x4	x4	x4	x4
For target devices in -1L, -1M, and -2L grades, certain link configurations and placements can be challenging for timing closure, in addition to generally increased challenge for high performance DMA / Bridge soft IP solutions. The IP customization GUI, by default, limits access to those link configurations even though they appear in this table. For more information, see Answer Record 000035682 for general guidance on selecting link configurations and placements for easier timing closure, and for specific guidance on accessing link configurations which are access limited by default by the IP customization GUI. AMD advises you to review this answer record at the start of project planning and prior to the start of board schematic capture. PL PCIE5 PCIe Gen5 support is available only in Versal Premium, Versal Prime, Versal HBM, and Versal AI Core series.