Gen1 (2.5 GT/s per lane) |
x16 |
x16 |
x16 |
x16 |
x16 |
x16 |
Gen2 (5 GT/s per lane) |
x16 |
x16 |
x16 |
x16 |
x16 |
x16 |
Gen3 (8 GT/s per lane) |
x16 |
x16 |
x16 |
x16 |
x16 |
x16 |
Gen4 (16 GT/s per lane) |
x8 |
x8 |
x8 |
x8 |
x8 |
x8 |
Gen5 (32 GT/s per lane)
2
|
N/A |
N/A |
x4 |
x4 |
x4 |
x4 |
- For target devices in -1L, -1M, and -2L grades,
certain link configurations and placements can be challenging
for timing closure, in addition to generally increased challenge
for high performance DMA / Bridge soft IP solutions. The IP
customization GUI, by default, limits access to those link
configurations even though they appear in this table. For more
information, see Answer Record 000035682 for
general guidance on selecting link configurations and placements
for easier timing closure, and for specific guidance on
accessing link configurations which are access limited by
default by the IP customization GUI. AMD advises you to review this answer record at
the start of project planning and prior to the start of board
schematic capture.
- PL PCIE5 PCIe Gen5 support is available only in Versal Premium, Versal Prime, Versal
HBM, and Versal AI Core series.
|