The Verilog test model used for the Root Port Model lets you specify the name of the test to be run as a command line parameter to the simulator.
To change the test to be run, change the TESTNAME value, which
is defined in the test files sample_tests1.v and
pio_tests.v. This mechanism is used for Mentor
Graphics Advanced Simulator. The Vivado simulator uses the -testplusarg option to specify TESTNAME. For example:
demo_tb.exe-gui -view wave.wcfg -wdb wave_isim -tclbatch isim_cmd.tcl
-testplusarg TESTNAME=sample_smoke_test0