Configuration Management Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The ports used by Configuration Management Interface is described in Configuration Management Interface. Root Ports must use the Configuration Management Interface to set up the Configuration Space. Endpoints can also use the Configuration Management Interface to read and write; however, care must be taken to avoid adverse system side effects.

The user application must supply the address as a Dword address, not a byte address.

Tip: To calculate the Dword address for a register, divide the byte address by four.

For example:

For the Command/Status register in the PCI Configuration Space Header:

  • The Dword address of is 01h.
    Note: The byte address is 04h.
For BAR0:
  • The Dword address is 04h.
    Note: The byte address is 10h.

To read any register in configuration space, the user application drives the register Dword address onto cfg_mgmt_addr[9:0]. cfg_mgmt_function_number[7:0] selects the PCI Function associated with the configuration register. The core drives the content of the addressed register onto cfg_mgmt_read_data[31:0]. The value on cfg_mgmt_read_data[31:0] is qualified by signal assertion on cfg_mgmt_read_write_done. The following figure illustrates an example with read from the Configuration Space.

Figure 1. cfg_mgmt_read_type0_type1

To write any register in configuration space, the user logic places the address on the cfg_mgmt_addr[9:0], the function number on cfg_mgmt_function_number[7:0], write data on cfg_mgmt_write_data, byte-valid on cfg_mgmt_byte_enable [3:0], and asserts the cfg_mgmt_write signal. In response, the core asserts the cfg_mgmt_read_write_done signal when the write is complete (which can take several cycles). The user logic must keep cfg_mgmt_addr, cfg_mgmt_function_number, cfg_mgmt_write_data, cfg_mgmt_byte_enable, and cfg_mgmt_write stable until cfg_mgmt_read_write_done is asserted. The user logic must also deassert cfg_mgmt_write in the cycle following the cfg_mgmt_read_write_done from the core.

Figure 2. cfg_mgmt_write_type0

When the core is configured in the Root Port mode, when you assert cfg_mgmt_debug_access input during a write to a Type-1 PCIe® Configuration register forces a write into certain read-only fields of the register.

Figure 3. cfg_mgmt_debug_access