- The user application first asserts
cfg_interrupt_intandcfg_interrupt_pendingto assert the interrupt. - The core asserts
cfg_interrupt_sentto indicate the interrupt is accepted. If the Interrupt Disable bit in the PCI Command register is set to 0, the core sends an assert interrupt message (Assert_INTA). After the interrupt has been serviced, the user applicationdeasserts cfg_interrupt_int. - After the user application
deasserts cfg_interrupt_int, the core sends a deassert interrupt message (Deassert_INTA). This is indicated by the assertion ofcfg_interrupt_senta second time.
cfg_interrupt_int must be asserted until
the user application receives confirmation of the assert interrupt message (Assert_INTA), which is indicated by the assertion of
cfg_interrupt_sent, and the interrupt has been
serviced/cleared by the Root's Interrupt Service Routine (ISR). Deasserting cfg_interrupt_int causes the core to send the deassert
interrupt message (Deassert_INTA). cfg_interrupt_pending must be asserted along with the
assertion of cfg_interrupt_int until the interrupt has
been serviced, otherwise, the interrupt status bit in the status register is not updated
correctly. cfg_interrupt_pending can be deasserted
along with the deassertion of cfg_interrupt_int after
the first assertion of cfg_interrupt_sent. When the
software/Root's ISR receives an assert interrupt message, it reads this interrupt status
bit to determine whether there is an interrupt pending for this function.
cfg_function_status to check whether INTx interrupts are
enabled or disabled, and assert cfg_interrupt_int only
if interrupts are enabled in the command register.