Legacy Interrupt Mode - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
  • The user application first asserts cfg_interrupt_int and cfg_interrupt_pending to assert the interrupt.
  • The core asserts cfg_interrupt_sent to indicate the interrupt is accepted. If the Interrupt Disable bit in the PCI Command register is set to 0, the core sends an assert interrupt message (Assert_INTA). After the interrupt has been serviced, the user application deasserts cfg_interrupt_int.
  • After the user application deasserts cfg_interrupt_int, the core sends a deassert interrupt message (Deassert_INTA). This is indicated by the assertion of cfg_interrupt_sent a second time.

cfg_interrupt_int must be asserted until the user application receives confirmation of the assert interrupt message (Assert_INTA), which is indicated by the assertion of cfg_interrupt_sent, and the interrupt has been serviced/cleared by the Root's Interrupt Service Routine (ISR). Deasserting cfg_interrupt_int causes the core to send the deassert interrupt message (Deassert_INTA). cfg_interrupt_pending must be asserted along with the assertion of cfg_interrupt_int until the interrupt has been serviced, otherwise, the interrupt status bit in the status register is not updated correctly. cfg_interrupt_pending can be deasserted along with the deassertion of cfg_interrupt_int after the first assertion of cfg_interrupt_sent. When the software/Root's ISR receives an assert interrupt message, it reads this interrupt status bit to determine whether there is an interrupt pending for this function.

Note: For PCIE4C block, INTx interrupts are not blocked by the core when the interrupt disable bit is set in command register, for example,Command Register bit 10 = 1. The user application must monitor cfg_function_status to check whether INTx interrupts are enabled or disabled, and assert cfg_interrupt_int only if interrupts are enabled in the command register.
Figure 1. Legacy Interrupt Signaling