Configuration Space - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The PCI configuration space consists of the following primary parts, illustrated in the following tables. They include:

Legacy PCI v3.0 Type 0/1 Configuration Space Header
  • Type 0 Configuration Space Header used by Endpoint applications (see Table 1)
  • Type 1 Configuration Space Header used by Root Port applications (see Table 1)
Legacy Extended Capability Items
  • PCIe Capability Item
  • Power Management Capability Item
  • Message Signaled Interrupt (MSI) Capability Item
  • MSI-X Capability Item (optional)

The core implements up to four legacy extended capability items.

For more information about enabling this feature, see Customizing and Generating the Core.

The core can implement up to ten PCI Express Extended Capabilities. The remaining PCI Express Extended Capability Space is available for users to implement. The starting address of the space available to users begins at 600h when extended large is selected, and E00h when extended small is selected. If you choose to implement registers in this space, you can select the starting location of this space, and this space must be implemented in the user application.

Table 1. PCI Config Space Header (Type 0 and 1)
Byte Offset Register (Type 0: Endpoint) Register Type 1: Root/DS Port)
00h Device ID Vendor ID same as Endpoint
04h Status Command
08h Class Code Rev ID
0Ch BIST Header Lat Tim CacheL
10h BAR0
14h BAR1
18h BAR2 SecLTim SubBus# SecBus# PrimBus#
1Ch BAR3 Secondary Status I/O Lim I/O Base
20h BAR4 Memory Limit Memory Base
24h BAR5 PrefetchMemLimit PrefetchMemBase
28h Cardbus CIS Pointer Prefetchable Base Upper 32 Bits
2Ch Subsystem ID Subsystem Vendor ID Prefetchable Limit Upper 32 Bits
30h Expansion ROM BAR I/O Limit Upper 16 I/O Base Upper 16
34h Reserved CapPtr Reserved CapPtr
38h Reserved Expansion ROM BAR
3Ch Max_Lat Min_Gnt IntrPin IntrLine Bridge Control IntrPin IntrLine
Table 2. PCI Express Config Space
Byte Offset (DW Offset) Register (Endpoint) Register (Root/DS Port)
40h (10h) PM Capability NxtCap PM Cap ID same as Endpoint
44h (11h) Data BSE PMCSR
48h (12h) MSI Control NxtCap MSI Cap ID
4Ch (13h) Message Address (Lower)
50h (14h) Message Address (Upper)
54h (15h) Reserved Message Data
58h (16h) Mask Bits
5Ch (17h) Pending Bits
60h (18h) MSIX Control NxtCap MSIX Cap ID Reserved
64h (19h) Table Offset Table BIR Reserved
68h (1Ah) PBA Offset PBA BIR Reserved
6Ch (1Bh) Reserved Reserved
70h (1Ch) PCIE Capability NxtCap PCIE Cap ID same as Endpoint
74h (1Dh) Device Capabilities
78h (1Eh) Device Status Device Control
7Ch (1Fh) Link Capabilities
80h (20h) Link Status Link Control
84h (21h) Reserved Slot Capabilities
88h (22h) Reserved Slot Status Slot Control
8Ch (23h) Reserved Root Capabilities 1 Root Control 1
90h (24h) Reserved Root Status 1
94h (25h) Device Capabilities 2 same as Endpoint
98h (26h) Device Status 2 Device Control 2
9Ch (27h) Link Capabilities 2
A0h (28h) Link Status 2 Link Control 2
A4-FCh

Unimplemented Configuration Space

(Returns 00000000h)

  1. Root Port only; Reserved in Switch DS Ports.
Table 3. PCIe Capability Order with PCIE4 Capabilities
PF0 PF1-3 VF Start Address PF0 Next Pointer
Legacy PCI CSH Legacy PCI CSH Legacy PCI CSH 0x00 0x40
PM PM - 0x40 0x48
MSI MSI - 0x48 0x60
MSI-X MSI-X MSI-X 0x60 0x70
PCIE PCIE PCIE 0x70 0x0
Extend Extend   0xB0  
Table 4. PCI Express Extended Configuration Space: Byte Offset 100h (40h) to 32Ch
Byte Offset (DW Offset) Register (Endpoint) Register (Root Port)
100h (40h) Nxt Cap Cap Ver AER Ext Cap same as Endpoint
104h (41h) Uncorrectable Error Status Register
108h (42h) Uncorrectable Error Mask Register
10Ch (43h) Uncorrectable Error Severity Register
110h (44h) Correctable Error Status Register
114h (45h) Correctable Error Mask Register
118h (46h) Advanced Error Cap. & Control Register
11Ch (47h) Header Log Register 1
120h (48h) Header Log Register 2
124h (49h) Header Log Register 3
128h (4Ah) Header Log Register 4
12Ch (4Bh) Reserved Root Error Command Register
130h (4Ch) Reserved Root Error Status Register
134h (4Dh) Reserved Error Source ID Register
140h (50h) Nxt Cap Cap Ver SR-IOV Ext Cap Reserved
144h (51h) Capability Register
148h (52h) SR-IOV Status Control
14Ch (53h) Total VFs Initial VFs
150h (54h) Func Dep Link Number VFs
154h (55h) VF Stride First VF Offset
158h (56h) VF Device ID Reserved
15Ch (57h) Supported Page Sizes
160h (58h) System Page Size
164h (59h) VF Base Address Register 0
168h (5Ah) VF Base Address Register 1
16Ch (5Bh) VF Base Address Register 2
170h (5Ch) VF Base Address Register 3
174h (5Dh) VF Base Address Register 4
178h (5Eh) VF Base Address Register 5
180h (60h) Nxt Cap Cap Ver ARI Ext Cap
184h (61h) Control NxtFn FnGrp
188h - 19Ch Reserved
1A0h (68h) Nxt Cap Cap Ver DSN Ext Cap
1A4h (69h) Device Serial Number (First)
1A8h (6Ah) Device Serial Number (Second)
1ACh - 1BCh Reserved
1C0h (70h) Nxt Cap Cap Ver Second PCIE Ext Cap same as Endpoint
1C4h (71h) Lane Control
1C8h (72h) Reserved Lane Error Status
1CCh (73h) Lane 1 Eq Ctrl Reg Lane 0 Eq Ctrl Reg
1D0h (74h) Lane 3 Eq Ctrl Reg Lane 2 Eq Ctrl Reg
1D4h (75h) Lane 5 Eq Ctrl Reg Lane 4 Eq Ctrl Reg
1D8h (76h) Lane 7 Eq Ctrl Reg Lane 6 Eq Ctrl Reg
1DCh (77h) Lane 9 Eq Ctrl Reg Lane 8 Eq Ctrl Reg
1E0h (78h) Lane 11 Eq Ctrl Reg Lane 10 Eq Ctrl Reg
1E4h (79h) Lane 13 Eq Ctrl Reg Lane 12 Eq Ctrl Reg
1E8h (7Ah) Lane 15 Eq Ctrl Reg Lane 14 Eq Ctrl Reg
1ECh (7Bh) Reserved
1F0h (7Ch) Nxt Cap Cap Ver VC Ext Cap
1F4h (7Dh) Port VC Capability Register 1
1F8h (7Eh) Port VC Capability Register 2
1FCh (7Fh) Port VC Status Reserved
200h(80h) VC Resource Capability Register 0
204h(81h) VC Resource Control Register 0
208h(82h) VC Resource Stat 0
20Ch(83h) VC Resource Capability Register 1
210h (84h) VC Resource Control Register 1
214h (85h) VC Resource Stat 1
218h (86h) Reserved
21Ch (87h)
Table 5. PCI Express Extended Configuration Space: Byte Offset 330h (CCh) to FFCh
Byte Offset (DW Offset) Register (Endpoint) Register (Root Port)
330h (CCh) Reserved Nxt Cap Cap Ver Loopback VSEC
334h (CDh) Loopback Header
338h (CEh) Loopback Control
33Ch (CFh) Loopback Status
340h (D0h) Error Count 1
344h (D1h) Error Count 2
348h (D2h) Error Count 3
34Ch (D3h) Error Count 4
380h (E0h) Nxt Cap Cap Ver ATS Ext Cap Reserved
384h (E1h) Control Reg Capability Reg
388-38Ch Reserved
390h (E4h) Nxt Cap Cap Ver PRI Ext Cap
394h (E5h) Status Reg Control Reg
398h (E6h) Outstanding Page Request Capacity
39Ch (E7h) Outstanding Page Request Allocation
3A0h (E8h) Nxt Cap Cap Ver DL Feature Ext Cap same as Endpoint
3A4h (E9h) Capabilities Register
3A8h (EAh) Status Register
3ACh (EBh) 1 DW Reserved
3B0h (ECh) Nxt Cap Cap Ver 16 GT/s Capability
3B4h (EDh) Capabilities Register
3B8h (EEh) Control Register
3BCh (EFh) Status Register
3C0h (F0h) Local Data Parity Mismatch Register
3C4h (F1h) First Retimer Data Parity Mismatch Status Register
3C8h (F2h) Second Retimer Data Parity Mismatch Status Register
3CCh (F3h) Lane 3-0 Eq Control Register
3D0h (F4h) Lane 7-4 Eq Control Register
3D4h (F5h) Lane 11-8 Eq Control Register
3D8h (F6h) Lane 15-12 Eq Control Register
3DCh- 3FCh 5 DW Reserved
400h (100h) Nxt Cap Cap Ver Margining Ext Cap
404h (101h) Port Status Port Capabilities
408h (102h) Lane 0 Status Lane 0 Control
40Ch (103h) Lane 1 Status Lane 1 Control
410h (104h) Lane 2 Status Lane 2 Control
414h (105h) Lane 3 Status Lane 3 Control
418h (106h) Lane 4 Status Lane 4 Control
41Ch (107h) Lane 5 Status Lane 5 Control
420h (108h) Lane 6 Status Lane 6 Control
424h (109h) Lane 7 Status Lane 7 Control
428h (10Ah) Lane 8 Status Lane 8 Control
42Ch (10Bh) Lane 9 Status Lane 9 Control
430h (10Ch) Lane 10 Status Lane 10 Control
434h (10Dh) Lane 11 Status Lane 11 Control
438h (10Eh) Lane 12 Status Lane 12 Control
43Ch (10Fh) Lane 13 Status Lane 13 Control
440h (110h) Lane 14 Status Lane 14 Control
444h (111h) Lane 15 Status Lane 15 Control
448h-44Ch 2 DW Reserved
450h (114h) Nxt Cap Cap Ver ACS Ext Cap
454h (115h) ACS Control ACS Capabilties same as Endpoint
458h (116h) Egress Control Vector
45Ch 1 DW Reserved
460h – 4BCh PL 32 GT/s / Reserved
4C0h – 500h

17 DW Reserved

504h (141h) VC Arb Table
544h -5ECh 44 DW Reserved
5F0h (17Ch) PASID
600h-DE0h Extend-Large T& PDVSEC
DE4h-DFCh PER Msg
E00h-FFCh Extend-Small
Note: For PL-PCIE5, SRIOV capability starts at 148h instead of 140h and ARI capability starts at 188h instead of 180h.