| phy_txdetectrx |
O |
1 |
Tells the PHY to perform receiver detection when this
signal is High and POWERDOWN is in P1 low power state. Receiver
detection is complete when phystatus asserts for one pclk cycle. The
status of receiver detection is indicated in rxstatus when phystatus is
High for one pclk cycle.
- rxstatus = 000b: Receiver not present
- rxstatus = 001b: Receiver present
|
| phy_txelecidle |
O |
1 |
Forces the tx[p/n] to electrical idle when this
signal is High. During electrical idle, tx[p/n] are driven to the DC
common mode voltage. Per lane. |
| phy_txcompliance |
O |
1 |
Sets the running disparity to negative when this
signal is logic High. Used when transmitting the PCIe compliance pattern. Per
lane. |
| phy_rxpolarity |
O |
1 |
Requests the PHY to perform polarity inversion on the
received data when this signal is High. Per lane. |
| phy_powerdown[1:0] |
O |
2 |
Requests PHY to enter power saving state or return to
normal power state. Power management is complete when PHYSTATUS asserts
for one PCLK cycle.
- 00b: P0, normal operation.
- 01b: P0s, power saving state with low recovery
time latency.
- 10b: P1, power saving state with longer recovery
time latency.
- 11b: P2, lowest power state.
P2 is not supported. |
| phy_rate[1:0] |
O |
2 |
Requests the PHY to perform a dynamic rate change.
Rate change is complete when PHYSTATUS asserts for one PCLK cycle.
rxvalid, rxdata, and rxstatus must be ignored while the PHY is in rate
change.
- 00b: Gen1
- 01b: Gen2
- 10b: Gen3
In the simulation mode (PHY_SIM_EN = TRUE), PHY status assertion
takes about 45 μs for Gen3 speed change. |