Message Requests on the Requester Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The transfer of a message on the requester request interface is similar to that of a memory write request, except that a payload are not always be present. The transfer starts with the 128-bit descriptor, followed by the payload, if present. The first Dword of the payload must immediately follow the descriptor, regardless of the address alignment mode in use. The addr_offset[3:0] field in the s_axis_rq_tuser bus must be set to 0 for messages when the address-aligned mode is in use. The core determines the end of the payload from s_axis_rq_tlast and s_axis_rq_tkeep signals. The First Byte Enable and Last Byte Enable bits (first_be[7:0] and last_be[7:0]) are not used for message requests.