Maintaining Transaction Order - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The core does not change the order of requests received from the user on its requester interface when it transmits them on the link. In cases where the user logic would like to have precise control of the order of transactions sent on the requester request interface and the completer completion interface (typically to avoid Completions from passing Posted requests when using strict ordering), the core provides a mechanism for the user logic to monitor the progress of a Posted transaction through its pipeline, so that it can determine when to schedule a Completion on the completer completion interface without the risk of passing a specific Posted request transmitted from the requester request interface.

When transferring a Posted request (memory write transactions or messages) across the requester request interface, the user logic are provide an optional 6-bit sequence number to the PCIe® core in its first beat. The sequence number field seq_num0[5:0] within s_axis_rq_tuser is used to send the sequence number for the first TLP starting in the beat, and the field seq_num1[5:0] is used to send the sequence number for the second TLP starting in the beat (if present). The user logic can monitor the pcie_rq_seq_num0[5:0] and pcie_rq_seq_num1[5:0] outputs of the core for these sequence numbers to appear. When the transaction has reached a stage in the internal transmit pipeline of the core where a Completion is unable to pass it, the core asserts pcie_rq_seq_num_vld0 for one cycle and provides the sequence number of the Posted request on the pcie_rq_seq_num0[5:0] output. If there is a second Posted request in the pipeline in the same cycle, the core also asserts pcie_rq_seq_num_vld1 in the same cycle and provides the sequence number of the second Posted request on the pcie_rq_seq_num1[5:0] output. The user logic must therefore monitor both sets of the sequence number outputs to check if a specific TLP has reached the pipeline stage. Any Completions transmitted by the core after the sequence number has appeared on pcie_rq_seq_num0[5:0] or pcie_rq_seq_num1[5:0] is guaranteed not to pass the corresponding Posted request in the internal transmit pipeline of the core.